CVE-2026-23554 PUBLISHED

The Intel EPT paging code uses an optimization to defer flushing of any cached EPT state until the p2m lock is dropped, so that multiple modifications done under the same locked region only issue a single flush.

Freeing of paging structures however is not deferred until the flushing is done, and can result in freed pages transiently being present in cached state. Such stale entries can point to memory ranges not owned by the guest, thus allowing access to unintended memory regions.

Xen 4.17 and onwards are vulnerable. Xen 4.16 and older are not vulnerable.

Only x86 Intel systems with EPT support are vulnerable.

Only x86 HVM/PVH guests using HAP can leverage the vulnerability on affected systems.

There are no mitigations.

• This issue was discovered by Roger Pau Monné of XenServer. finder

• https://xenbits.xenproject.org/xsa/advisory-480.html

• Privilege escalation, Denial of Service (DoS) affecting the entire host, and information leaks.