In the Linux kernel, the following vulnerability has been resolved:
iommu/vt-d: Clear Present bit before tearing down scalable-mode context entry
device_pasid_table_teardown() zeroes the 128-bit scalable-mode context
entry with context_clear_entry() while the Present bit is still set. This
creates a window where the hardware can fetch a torn entry, with some
fields already zeroed while Present is still set, leading to unpredictable
behavior or spurious faults. The context-cache invalidation is issued only
after the entry has been zeroed, and intel_pasid_free_table() then frees
the PASID directory pages, so the IOMMU can keep walking a stale Present=1
entry that points at freed memory.
While x86 provides strong write ordering, the compiler may reorder the two
64-bit writes to the entry, and the hardware fetch is not guaranteed to be
atomic with respect to multiple CPU writes.
Commit c1e4f1dccbe9d ("iommu/vt-d: Clear Present bit before tearing down
context entry") fixed this exact pattern in domain_context_clear_one() and
the copied-context path, but device_pasid_table_teardown() was not
converted.
Align it with the "Guidance to Software for Invalidations" in the VT-d
spec, Section 6.5.3.3, using the same ownership handshake as the sibling
fix: clear only the Present bit, flush it to the IOMMU, perform the
context-cache invalidation, and only then zero the rest of the entry.
CVSS Vector: CVSS:3.1/AV:L/AC:L/PR:N/UI:N/S:C/C:H/I:H/A:H
CVSS Score: 9.3
AV:L - The flaw is in Intel VT-d scalable-mode PASID context teardown reached only via local kernel IOMMU device-release paths (intel_iommu_release_device → device_pasid_table_teardown), triggered by PCI hot-unplug, sysfs driver unbind, or iommu deinit—not by any network-facing protocol.
AC:L - This is a use-after-free where intel_pasid_free_table() frees PASID directory pages while the IOMMU may still cache a Present=1 context entry; an attacker controlling a PASID-capable device can keep DMA active and time bus removal/teardown to hit the stale-entry window reliably (AC:L per UAF guidance).
PR:N - A malicious PASID-capable PCIe device can trigger the vulnerable intel_iommu_release_device teardown by physical hot-unplug (pci_stop_and_remove_bus_device) while sustaining DMA, requiring no authenticated host account or capability on the target system.
UI:N - No victim interaction is required beyond the attacker's own device removal or driver-unbind orchestration; the vulnerable teardown executes automatically once the PCI/IOMMU release path runs.
S:C - A stale or torn scalable-mode context entry breaks VT-d DMA isolation—the IOMMU can translate device DMA against freed PASID table memory, crossing the device/host (or guest/host) IOMMU security boundary per kernel IOMMU bypass guidance.
C:H - With the IOMMU walking freed PASID directory pages, a controlled device can DMA-read host physical memory outside its assigned domain, yielding arbitrary cross-boundary read disclosure (C:H; UAF enables attacker influence over translation contents).
I:H - The same mistranslation gives the device an arbitrary DMA write primitive against host memory outside its domain, enabling data modification and potential control-flow hijack via memory corruption (standard UAF/IOMMU-bypass I:H guidance).
A:H - The commit documents unpredictable behavior and spurious DMAR faults from torn Present entries; freed PASID tables under active IOMMU walks can fault-storm, hang, or panic the host—any kernel crash/UAF qualifies as A:H.
| Attack Vector |
Local |
Scope |
Changed |
| Attack Complexity |
Low |
Confidentiality Impact |
High |
| Privileges Required |
None |
Integrity Impact |
High |
| User Interaction |
None |
Availability Impact |
High |
AV:L - The flaw is in Intel VT-d scalable-mode PASID context teardown reached only via local kernel IOMMU device-release paths (intel_iommu_release_device → device_pasid_table_teardown), triggered by PCI hot-unplug, sysfs driver unbind, or iommu deinit—not by any network-facing protocol.
AC:L - This is a use-after-free where intel_pasid_free_table() frees PASID directory pages while the IOMMU may still cache a Present=1 context entry; an attacker controlling a PASID-capable device can keep DMA active and time bus removal/teardown to hit the stale-entry window reliably (AC:L per UAF guidance).
PR:N - A malicious PASID-capable PCIe device can trigger the vulnerable intel_iommu_release_device teardown by physical hot-unplug (pci_stop_and_remove_bus_device) while sustaining DMA, requiring no authenticated host account or capability on the target system.
UI:N - No victim interaction is required beyond the attacker's own device removal or driver-unbind orchestration; the vulnerable teardown executes automatically once the PCI/IOMMU release path runs.
S:C - A stale or torn scalable-mode context entry breaks VT-d DMA isolation—the IOMMU can translate device DMA against freed PASID table memory, crossing the device/host (or guest/host) IOMMU security boundary per kernel IOMMU bypass guidance.
C:H - With the IOMMU walking freed PASID directory pages, a controlled device can DMA-read host physical memory outside its assigned domain, yielding arbitrary cross-boundary read disclosure (C:H; UAF enables attacker influence over translation contents).
I:H - The same mistranslation gives the device an arbitrary DMA write primitive against host memory outside its domain, enabling data modification and potential control-flow hijack via memory corruption (standard UAF/IOMMU-bypass I:H guidance).
A:H - The commit documents unpredictable behavior and spurious DMAR faults from torn Present entries; freed PASID tables under active IOMMU walks can fault-storm, hang, or panic the host—any kernel crash/UAF qualifies as A:H.
CVSS 3.1