CVE-2026-80727 PUBLISHED

x86/mce: Set up the polling timer before CMCI discovery

Assigner: Linux
Reserved: 26.08.2026 Published: 03.09.2026 Updated: 03.09.2026

In the Linux kernel, the following vulnerability has been resolved:

x86/mce: Set up the polling timer before CMCI discovery

I hit the following on one of my machines:

mce: CPU0 BANK15 CMCI inherited storm ------------[ cut here ]------------ ODEBUG: assert_init not available (active state 0) object: (_ptrval_) object type: timer_list hint: 0x0 WARNING: lib/debugobjects.c:632 at debug_object_assert_init+0x178/0x230, CPU#0: swapper/0/0 CPU: 0 UID: 0 PID: 0 Comm: swapper/0 Not tainted 7.2.0-rc5 #3 PREEMPTLAZY RIP: 0010:debug_object_assert_init+0x18f/0x230 Call Trace: <TASK> __mod_timer mce_timer_kick cmci_discover intel_init_cmci mce_intel_feature_init mcheck_cpu_init identify_cpu identify_boot_cpu arch_cpu_finalize_init start_kernel

A second splat follows right after, from timer_setup() finding that same timer already queued:

ODEBUG: init active (active state 0) object: (_ptrval_) object type: timer_list hint: stub_timer+0x0/0x10

This is happening because CMCI storm detection is trying to modify the timer before latter was properly set up.

Set up the timer first. __mcheck_cpu_setup_timer() only calls timer_setup(), and depends on neither the generic nor the vendor init.

[ bp: Massage commit message. ]

Product Status

Vendor Linux
Product Linux
Versions Default: unaffected
  • affected from 1f68ce2a027250aeeb1756391110cdc4dc97c797 to 17ab68d0cf6a41bff61b1e13c6141d9e463736ae (excl.)
  • affected from 1f68ce2a027250aeeb1756391110cdc4dc97c797 to e708fc1566ebd4a2d3f2546e6310d64d362db80d (excl.)
  • affected from 1f68ce2a027250aeeb1756391110cdc4dc97c797 to 4f4cba3947d2f0eceb32727e198ca2c149a653a9 (excl.)
  • affected from 1f68ce2a027250aeeb1756391110cdc4dc97c797 to a213dfaa2596c1c0dc4dae91c14fbfa499c03223 (excl.)
Vendor Linux
Product Linux
Versions Default: affected
  • Version 6.8 is affected
  • unaffected from 0 to 6.8 (excl.)
  • unaffected from 6.12.105 to 6.12.* (incl.)
  • unaffected from 6.18.45 to 6.18.* (incl.)
  • unaffected from 7.1.9 to 7.1.* (incl.)
  • unaffected from 7.2 to * (incl.)

References